The present invention relates to buffering data between a cache and a slower storage, and in particular to the provision of data from the buffer directly to the host.
Storage caches have long been used to provide data to a processor very quickly. The speed at which data is provided, and the cost of the cache seem to go up together, so it is expensive to provide a large cache. The cache is usually provided between a slower random access memory such as a large main storage, and the processor. In some prior art systems, a small buffer has been provided between the cache and main storage. The buffer has been used to provide the data to the processor at the same time that it is being written into the cache as in U.S. Pat. Nos. 4,189,770 and 3,820,078. In this manner, the processor does not have to wait for the data to be written into the cache. This approach has the disadvantage that the cache can not be working on a further storage request until the data from the buffer has been written into the cache.
Other problems associated with caches include portions of the cache becoming inoperable. If a portion of the cache which corresponds to a range of storage in main storage is bad, the cache becomes worthless for that range of storage. In such a case, the section of cache is deleted from use as in U.S. Pat. Nos. 3,800,292; 4,464,717; 3,820,078 and IBM TDB Vol. 23, No. 9 dated February 1981 titled "Cache Reconfiguration." In the IBM TDB, spare portions of the cache can be mapped to replace failed portions. However, once there are no spare portions available, the cache can not be used.